Traditional measures such as TDP (thermal design power) or CPU architecture-specific benchmarks are no longer good predictors of actual chip power consumption, several computer science professors have charged. Their paper, which will be presented at an Association for Computing Machinery conference in March, advises chipmakers to expose their CPUs' power metering to programmers -- something Intel has already done with its "Sandy Bridge" CPUs.

Several computer science professors have conducted a study that's being billed as "the first to systematically measure and analyze application power, performance, and energy on a wide variety of hardware." They're Kathryn McKinley (below left) of the University of Texas at Austin and Stephen Blackburn (below right) of the Australian National University, assisted by graduate students Hadi Esmaeilzadeh, Ting Cao, and Xi Yang.


Study authors Kathryn McKinley (left) and Stephen Blackburn (right)

Their paper, "Looking Back on the Language and Hardware Revolutions: Measured Power, Performance, and Scaling," will be presented in early March at the ACM's ASPLOS (Architectural Support for Programming Languages and Operating Systems) 2011 conference in Newport Beach, California, but it's already available in PDF format. In it, the authors report measuring the power consumption of eight IA32 processors, manufactured by Intel from 2003 to 2010: the 130nm Pentium 4, the 65nm Core 2 Duo, the 45nm Atom, and the 32nm Core i5.

These processors all had isolated processor power supplies on the motherboard, so Hall-effect sensors could be used to measure power supply current (unfortunately, this precluded measuring the 90nm Pentium M). According to the authors, actual power measurements varied widely from benchmark to benchmark: Furthermore, they add, relative performance, power, and energy were not well predicted by core count, clock speed, or reported Thermal Design Power (TDP), i.e., the nominal amount of power the chip is designed to dissipate without exceeding the maximum junction temperature.

Processors tested, with manufacturer power specs
(Click to read)

The authors point out that, for example, the 65nm and 45nm Core 2 Duo processors they tested (see table above) both have a 65 Watt TDP. However, their measured power actually differs by around 40 to 50 percent (see table below).

Processors tested, with actual measured power
(Click to read)

Processors were tested for power consumption using both native benchmarks -- SPE CPU2006, for example -- and managed (Java) workloads. According to the authors, the power, performance, and energy trends of native workloads do not approximate managed workloads: "For example, (a) the SPEC CPU2006 native benchmarks on the i7 (45) and i5 (32) draw significantly less power than managed or scalable native benchmarks; and (b) managed runtimes exploit parallelism even when running single-threaded applications."

Features such as clock scaling, TurboBoost, SMT (simultaneous multithreading), and CMP (core count) have an effect on CPU power consumption that is still "complex and poorly understood," the paper adds. As an example, the authors cite the following:

• halving the clock rate of the Core i5 (32nm) increases its energy consumption around 4 percent, whereas it decreases the energy consumption of the Core i7 (45nm) and Core 2 Duo (45nm) by around 60 percent
• i.e., running the i5 (32nm) at its peak clock rate is as energy-efficient as running it at its lowest, whereas running the i7 and Core 2 Duo at their lowest clock rate is substantially more energy efficient than their peak

Other interesting findings cited in the paper include:

• A die shrink is remarkably effective at reducing energy consumption, even when controlling for clock frequency
• When comparing one core to two, enabling a second core is not consistently energy-efficient
• SMT delivers substantial energy savings for the Core i5 and Atom

The authors conclude that researchers need to be sure they test processor power consumption with both native and managed workloads. For their part, manufacturers should make sure to expose their on-chip power meters to the community, the paper adds.


Intel's "Sandy Bridge" processors already expose their on-chip power metering
(Click to enlarge)

Co-author McKinley is quoted in a release as saying, "In the past, we optimized only for performance. If you were picking between two software algorithms, or chips, or devices, you picked the faster one. You didn’t worry about how much power it was drawing from the wall socket. There are still many situations today -- for example, if you are making software for stock market traders -- where speed is going to be the only consideration. But there are a lot of other areas where you really want to consider the power usage."

Jonathan Angel can be reached at jonathan.angel@ziffdavisenterprise.com and followed at www.twitter.com/gadgetsense.

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